The invention relates to bit map scanning devices, and particularly to bitmap memories and controllers for laser printers.
Bit map scanning devices, such as laser printers, process data defining a two-dimensional element-by-element map of an image for printing or displaying. Such scanning devices typically employ a raster scanning technique, in which images are defined by lines of picture elements (pixels), scanned one line at a time.
Many laser printers employ a bitmap memory in which an image is composed pixel by pixel and then sequentially scanned and synchronously sent to the imaging print engine. One advantage of the bitmap technique is that no data will be missing on a printed page due to a lack of processing power, because every image is completely composed before it prints. Modern laser printers, however, have resolutions on the order of 300 to 600 dots per inch (DPI). Very large amounts of memory are required to implement bitmaps at these resolutions: for example, an A4 sized page at 300 DPI consumes at least 1 megabyte of memory. Furthermore, the bitmap memory must be processed at a very high rate of speed to keep up with the raster scanner. In addition, the bitmap memory must be capable of being nearly simultaneously filled with picture element data by an image generating processor while a print engine controller scans the data out of the bitmap to be serialized and forwarded to the print engine. There should also be provided some means for refreshing the bitmap memory to guarantee data retention. All of these factors lead to complexity in the implementation of bitmap controllers.
There are several approaches to implementing bitmap memory controllers. On the high performance end, graphic pipeline architectures using multi-stage processors are employed. A system CPU and a system memory are provided for handling system operations. Multiple pages of dual port bitmap memory are also provided, separate from the system memory. The bitmap memory is directly connected to the output of a graphic processor, which performs graphic and bitmap manipulations separately and in parallel with system CPU operations. Such implementations maximize bitmap memory bandwidth thereby providing very high performance; however, they are very expensive.
Lower cost, lower performance implementations employ a general purpose microprocessor system. The system CPU performs general purpose operations as well as graphic and bitmap manipulations, and part of the system memory is allocated to store the bitmap data. Since there are no other processors to share the workload, the system and memory busses are subjected to huge flows of bitmap data, greatly restricting printer performance and rendering such implementations undesirable.
A more particular problem affecting laser printer bitmap controllers involves high speed clearing of the bitmap. Printers supporting certain algorithms such as Postscript.RTM. are required to clear (or write to binary `0`) the bitmap after a page has been scanned out in order to facilitate the writing of a new page. Clearing large amounts of memory takes a significant amount of time, thus contributing to performance problems. The complexity of bitmap controllers is further increased where high speed bitmap clearing modes are implemented.
It would be advantageous to provide a low cost printer employing a single general purpose microprocessor architecture which also provides high performance. In particular, it is desirable to implement a bitmap memory controller for a single processor system which allows efficient and high speed control of bitmap refresh and dual port accesses, while providing a fast and efficient means for clearing the bitmap.